This trace mode supports single or dual channel continuous analogue data capture and optional enhanced edge trigger logic.

At the start of trace state 3 (ie, after the trigger), this mode implements channel alt between the primary to the secondary channel. If both channels are programmed with the same input and attenuation, data capture is effectively single channel. If each trace channel is programmed with a different input (and possibly attenuation), data capture is dual channel.

The Pre Trigger Delay (trace state 1) is also implemented in this mode.

During this state and state 2 only the primary channel is captured and channel is disabled. This ensures the trigger logic works correctly. The pre trigger delay is computed as:

T[PRE] = 10 + PRETD * (7 + 3 * (TB+1))

T[PRE]	pre trigger delay (in PIC cycles).
PRETD	8 pre trigger delay value (R20 -> 0 to 255).
TB	8 bit time-base expansion (R13 -> 1 to 256, 0 read as 256).

The minimum pre trigger delay is 1.2 uS and the maximum 79.3572 mS.

There is a latency of 5 to 9 PIC cycles from the trigger to the switch to the secondary channel.

The analog trigger configuration is enhanced and supports an optional edge trigger.

The post trigger delay is calculated as:

T[PTD] = 10 + 5 * N[swap] + U

N[swap] = (PTD + 1) * (TB + 2) + PTD[hi] + 1

where:

T[PTD]	post trigger delay (in PIC cycles).
PTD	16 bit post trigger delay value (R11, R12 -> 0 to 65536).
PTD[hi]	8 bit high byte of post trigger delay (R11 -> 0 to 255).
TB	8 bit time-base expansion (R13 -> 1 to 256, 0 read as 256).
U	trigger uncertainty = ± 2 PIC cycles

The minimum post trigger delay is 12 uS ± 0.8 uS and the maximum 33.817092 S ± 0.8 uS and the sample clock is stopped 3 PIC cycles after the last channel chop.